Conventional synchronous communication devices include, for instance, the family communication system described in Japanese Unexamined Patent Application Laid-open No. H02-041190. This family communication system is a system for carrying out communication between at least two family computers connected via a communication line, the system comprising means for correcting the time lag of data inputted through an input unit of each family computer, wherein repeatedly generated number codes in synchrony with a key scan pulse are transmitted to a partner side device, the time lag being corrected at the partner side using the number code.
FIG. 16 is a timing chart explaining the timing of data in the above-described family computer communication system. The operation of this family computer communication system will be explained with reference to FIG. 1.
In FIG. 16, (a) and (b) denote respectively a key scan pulse generated by each family computer. The state of the keyboard is acquired, by the family computer, in the form of data through these key scan pulses (a) and (b). When a communication adapter is used, as illustrated in (c) and (d), a delay corresponding to the time between the instants t1 to t2 and t3 to t4 occurs during data transmission to the modem of the partner side. When two family computers are gaming simultaneously, it becomes necessary to send to the family computers the data pair denoted in the figure by m and n, in a correct sequence. That is, the data of the player captured at the time of the pulse m, and the data of the partner captured at the time of the pulse n must be inputted to the respective family computer in the right sequence.
As a result of communication delay, data is inputted in FIG. 16 from the first to the second family computer at the time of the pulse n+3, while at the time of the pulse m+3, data is inputted from the second to the first family computer. When for instance transmission of data captured at timings m and n is delayed up to timings m+3 and n+3, the data sent to both family computers becomes a data pair delayed by 3 pulses each.
The two family computers are not limited to have their power turned on simultaneously, and hence the time difference between m and n changes by 1 pulse at the highest. Thus, upon reaching N pulses, the data at the time m is sent to the partner side at the time N+2, as illustrated in FIG. 1. However, data at the time N cannot arrive until the time m+4. When data is sent in this condition to the family computers, the required data is not received at the required time, and the two family computers end up operating separately. As the above makes clear, the delay occurring between family computers is the sum of the data communication delay and the key scan pulse delay.
The data communication delay depends on the hardware and on the communication speed, and hence is relatively fixed. The key scan pulse delay, however, varies in accordance with the timing with which the device is operated, and varies gradually as a result of the phase difference of the key scan pulses in the two devices. To correct this, number codes repeatedly generated in synchrony with the key scan pulses are sent to the partner side. The side receiving the number codes synchronizes own data to the content of the number code and transmits it.
To detect the delay, and to synchronize and send the data, the partner number code and the own number code are stored, and a timer is operated. The timer is stopped next with an own scan pulse, whereupon there is measured the delay from the input time of the partner data to the generation time of the own scan pulse. An average value is determined by repeating this operation several times. Delay is correctly detected by comparing this average value with a numerical value set beforehand.
A variable shift register is necessary for delaying own captured data by several pulses. For instance, if the data of the m pulse is sent to a family computer at m+3, a three-stage shift register is needed. The delay pulse count must be variable in order to track the changing key scan pulses.
In the above family computer communication system, briefly, information inputted at the N-th synchronization is used for information processing at the (N+m)th (m is an integer>0) synchronization, to prevent thereby loss of processing speed on account of communication delay.
In the above-described family computer system, however, waiting until information reception becomes necessary when no input information from the partner can be received within a predetermined time. As a result, synchronization processing becomes temporarily paused, which is annoying for the users that use the family computer system. When using a communication line in which communication quality is not assured, such as internet or the like, in particular, this is problematic in that temporary stops may occur every few seconds, dramatically detracting thereby from the value of the system.